Communication developments in the last decade have demonstrated what seems to be a migration from parallel data input/output (I/O) interface implementations to a preference for serial data I/O interfaces. Some of the motivations for preferring serial I/O over parallel I/O include reduced system costs through reduction in pin count, simplified system designs, and scalability to meet the ever increasing bandwidth requirements of today's communication needs. Serial I/O solutions will most probably be deployed in nearly every electronic product imaginable, including IC-to-IC interfacing, backplane connectivity, and box-to-box communications.
Although the need for increased communication bandwidth continues to drive future designs, support for the lower bandwidth legacy systems still remains. As such, the future designs are required to provide a wide range of scalability, whereby data rate, slew rate, and many other physical (PHY) layer attributes are adaptable. For example, a particular transmitter/receiver pair may be configured for use as both a high-definition serial digital interface (HD-SDI) and a standard-definition serial digital interface (SD-SDI). Both standards have similar specifications, but differ from each other at the PHY layer with respect to, for example, bit rate and edge rate. The same transmitter/receiver pair, however, may nevertheless be required to meet both specifications.
Added to the complexity of adapting today's communication systems to the plethora of communication protocols that are available, is the challenging task of mitigating the channel effects that are imposed upon the transmitted signal, such as intersymbol interference (ISI). Conventional techniques used to mitigate these ISI effects include the use of a decision feedback equalizer (DFE), which utilizes information obtained from previously received data bits to correct the currently received data bit.
In a typical DFE application, for example, a serial data path is sampled by a plurality of master-slave latches, whereby during the first half cycle, data bits are sampled, and during the second half cycle, data bits are stored. The stored data bits are then fedback to various taps of a summing junction, which adds or subtracts a scaled value of the stored data bits to the currently received data bit. As such, ISI caused by previously received data bits may be substantially subtracted from the currently received data bit.
As the data rate increases, however, the cycle time, or unit interval (UI), of each data bit shrinks, effectively decreasing the amount of time that is available to perform the DFE function. Efforts continue, therefore, to reduce the delay of the feedback loop, so that proper DFE operation may be sustained despite the ever decreasing UI time allocation.